View UPD61P24_5513.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD61P24
4-BIT SINGLE-CHIP MICROCONTROLLER FOR REMOTE CONTROL TRANSMISSION
DESCRIPTION
The PD61P24 is a 4-bit single-chip microcontroller for infrared remote controllers for TVs, VCRs, stereos, cassette decks, air conditioners, etc. As the PD61P24 is user-programmable, it is ideal for evaluation of programs running in a PD6124A or 6600A, and for small-scale production of such systems. The functions of the PD61P24 are described in detail in the following User's Manual. Be sure to read this manual before designing your system.
PD612X Series User's Manual: IEP-1083
FEATURES
* Transmitter for programmable infrared remote controller * 19 types of instructions * Instruction execution time: 17.6 s (with 455-kHz ceramic resonator) * On-chip one-time PROM: 1002 x 10 bits * Data memory (RAM) capacity * I/O pins (KI/O): 8 pins * Input pins (KI): 4 pins : 32 x 5 bits * 9-bit programmable timer: 1 channel * Serial input pins (S-IN): 1 pin * Transmission-in-progress indication pin (S-OUT): 1 pin * Transmit carrier frequency (REM) fOSC/12, fOSC/8 * Standby operation (HALT/STOP mode) * Low power consumption * Current consumption in STOP mode (TA = 25C) 1 A MAX. * Low-voltage operation: VDD = 2.2 to 5.5 V
Caution To use the NEC transmission format, ask NEC to supply the custom code. Do no use R0 when using a register as an operand of the branch instruction.
The information in this document is subject to change without notice. Document No. U12629EJ4V0DS00 (4th edition) Previous No. IC-2876 Date Published July 1997 N Printed in Japan
The mark
shows major revised points.
(c)
1997
PD61P24
ORDERING INFORMATION
Part Number Package 20-pin plastic shrink DIP (300 mil) 20-pin plastic SOP (300 mil)
PD61P24CS PD61P24GS
PIN CONFIGURATION (Top View)
(1) Normal operating mode (2) PROM programming mode
K I/O1 1 K I/O0 2 S-IN 3 S-OUT 4 REM 5 V DD 6 OSC-OUT 7 OSC-IN 8 VSS 9 AC 10
20 K I/O2 19 K I/O3 18 K I/O4 17 K I/O5 16 K I/O6 15 K I/O7 14 K I0 13 K I1 12 K I2 11 K I3
D1 1 D0 2 VPP 3 (Open) 4 (Open) 5 VDD 6 (Open) 7 CLK 8 VSS 9 (L) 10
20 D2 19 D3 18 D4 17 D5 16 D6 15 D7 14 MD0 13 MD1 12 MD2 11 MD3
Caution Round brackets ( ) indicate the pins not used in the PROM programming mode. L : Connect each of these pins to GND via a resistor (470 ). Open: Leave these pins open.
2
PD61P24
BLOCK DIAGRAM
ROM D.P. ROM D.P. PC(L) PC(H)
L H
1002 x 10 bits One-Time PROM (L) One-Time PROM (H) 32 x 5 bits SP ADD DEC M P X RAM RAM
CNTL CNTL (L) (H)
M P X
TIMER TIMER (L) (H) 10 bits OSC MOD
ALU
ACC
KEY KEY OUT(L) OUT(H)
KEY IN
Watchdog timer function
OSC-IN S-OUT REM OSC-OUT
S-IN
KI/O0-KI/O7
K I0 -KI3
AC
3
PD61P24
1. PROGRAM COUNTER (PC) ......... 10 BITS
The program counter (PC) is a binary counter, which holds the address information for the program memory. Figure 1-1. Program Counter Organization
PC 9
PC 8
PC 7
PC 6
PC 5
PC 4
PC 3
PC 2
PC 1
PC 0
PC
Normally, the program counter contents are automatically incremented each time an instruction is executed, according to the number of instruction bytes. When executing a jump instruction (JMP0, JC, JF), the program counter indicates the jump destination. Immediate data or the data memory contents are loaded to all or some bits of the PC. When executing the call instruction (CALL0), the PC contents are incremented (+1) and saved into the stack memory. Then, a value needed for each jump instruction will be loaded. When executing the return instruction (RET), the stack memory contents are double incremented (+2) and loaded into the PC. When "all clear" is input or on reset, the PC contents are cleared to "000H".
2.
STACK POINTER (SP) ......... 2 BITS
This 2-bit register holds the start address information for the stack area. The stack area is shared with the data
memory. The SP contents are incremented, when the call instruction (CALL0) is executed. They are decremented, when the return instruction (RET) is executed. The stack pointer is cleared to "00B" after reset or "all clear" is input, and indicates the highest address FH for the data memory as the stack area. The figure below shows the relationship for the stack pointer and the data memory area.
Data memory RC RD RE RF
(SP) 11B 10B 01B 00B
If the stack pointer overflows or underflows, it is determined that the CPU overflows, and the PC internal reset signal will be generated.
4
PD61P24
3. PROGRAM MEMORY (ROM) ......... 1002 STEPS x 10 BITS
The program memory (ROM) is configured in 10 bits steps. It is addressed by the program counter. Program and table data are stored in the program memory. Figure 3-1. Program Memory Map
000H 0FFH 100H 1FFH 200H 2FFH 300H 3E9H 3EAH 3FFH Test program area
4.
DATA MEMORY (RAM) ......... 32 WORDS x 5 BITS
The data memory is a RAM of 32 words x 5 bits. The data memory stores processing data. In some cases, the
data memory is processed in 8-bit units. R0 may be used as the data pointer for the ROM. After power application, the RAM will be undefined. The RAM retains the previous data on reset. Figure 4-1. Data Memory Organization
1
0 R0
. . .
RB RC . . . RF
SP-3 SP-2 SP-1 SP-0
Caution Avoid using the RAM areas RD, RE, and RF in a CALL routine as much as possible because these areas are also used as stack memory areas (to prevent program hang-up in case the value of the SP is destroyed due to some reason such as noise). When using these RAM areas as general-purpose RAM areas, be sure to include stack pointer checking in the main routine.
5
PD61P24
5. DATA POINTER (R0)
R0 (R10, R00) for the data memory can serve as the data pointer for the ROM. R0 specifies the low-order 8 bits in the ROM address. The high-order 2 bits in the ROM address are specified by the control register. Table referencing for ROM data can be easily executed by calling the ROM contents by setting the ROM address to the data pointer. On reset or "all clear" is input, it becomes undefined. Figure 5-1. Data Pointer Organization
Control registers (P1 ) AD9 AD 8 AD 7 AD 6
R10
R00
AD 5
AD 4
AD 3
AD 2
AD 1
AD 0
R0
6.
ACCUMULATOR (A) ......... 4 BITS
The accumulator (A) is a 4-bit register. The accumulator plays a major role in each operation. On reset or "all clear" is input, it becomes undefined. Figure 6-1. Accumulator Organization
A3
A2
A1
A0
A
7.
ARITHMETIC LOGIC UNIT (ALU) ......... 4 BITS
The arithmetic logic unit (ALU) is a 4-bit operation circuit, and executes simple operations, such as arithmetic
operations.
8.
FLAGS
(1) Status flag When the status for each pin is checked by the STTS instruction, if the condition coincides with the condition specified by the STTS instruction, the status flag (F) is set (to 1). On reset or "all clear" is input, it becomes undefined. (2) Carry flag When the INC (increment) instruction or the RL (rotate left) instruction is executed, if a carry is generated from the MSB for the accumulator, the carry flag (C) is set (to 1). The carry flag (C) is also set (to 1), if the contents for the accumulator are "FH", when the SCAF instruction is executed. On reset or "all clear" is input, it becomes undefined.
6
PD61P24
9. SYSTEM CLOCK GENERATOR
The system clock generator consists of a resonator, which uses a ceramic resonator (400kHz to 500kHz). Figure 9-1. System Clock Generator
OSC-IN
STOP mode
OSC-OUT
o System clock
In the STOP mode (oscillation stop HALT instruction), the oscillator in the system clock generator stops its operation, and the system clock o is stopped.
7
PD61P24
10. TIMER
The timer block determines the transmission output pattern. The timer consists of 10 bits, of which 9 bits serve as the 9-bit down counter and the remaining 1 bit serves as the 1-bit latch, which determines the carrier output validity. The 9-bit down counter is decremented (-1) every 8/fOSC(s) in synchronization with the machine cycle, after starting down count operation. Down counting stops after all of the 9 bits become 0. When down counting is stopped, the signal indicating that the timer operation has stopped, is output. If the CPU is at standby (HALT TIMER) for the timer operation completion, the standby (HALT) condition is released and the next instruction will be executed. If the next instruction again sets the value of the down counter, down counting continues without any error (the carrier output of the REM pin is not affected). Set the down count time according to the following calculation; (set value (HEX) + 1) x 8/fOSC. Setting the value to the timer is done by the timer manipulation instruction. When the down counter is operating, the remote control transmission carrier can be output to the REM pin. Whether or not to output the carrier can be selected by the MSB for the timer register block. Set "1", when outputting the carrier, or "0", when not outputting the carrier. If all the down counter bits become "0", when outputting the carrier, the carrier output will be stopped. When not outputting the carrier, the REM pin output will become low level. A signal in synchronization with the REM output is output to the S-OUT pin. However, the waveform for the SOUT pin is low, when the carrier is being output to the REM pin, or it is high, when the carrier is not being output to the REM pin. If the HALT instruction, which initiates the oscillation stop mode, is executed when the down counter is operating, the oscillation stop mode is initiated after down counting is stopped (after 0). Timer operation STOP/RUN is controlled by the control register (P1). (Refer to 13. CONTROL REGISTER (P1).) At reset (all clear) time, the REM pin goes low and S-OUT pin goes high. All 10 bits of the timer are cleared to 000H. Caution Because the timer clock is not synchronized with the carrier output, the pulse width may be shortened at the beginning and end of the carrier output. Figure 10-1. Timer Block Organization
Set by timer mainpulation instruction MSB 1/0 Clear Zero detection circuit 9-bit down counter fosc/8
S-OUT REM Carrier (fosc/12, fosc/8) Selected by control register
D 2 of control register P 1 (Timer RUN/STOP)
8
PD61P24
11. PIN FUNCTIONS
11.1 KI/O Pin (P0)
This is the 8-bit I/O pin for key-scan output. When the control register (P1) is set for the input port, the port can be used as an 8-bit input pin. When the port is set for the input mode, all of these pins are pulled down to the VSS level inside the LSI. At reset (all cleared), the value of I/O mode and output latch becomes undefined. Figure 11-1. KI/O Pin Organization
P10
P00
(P 1 ) Control register
P0
KI/O7
KI/O6
KI/O5
KI/O4
KI/O3
KI/O2
KI/O1
KI/O0
11.2
KI/O Pull-Down Resistor Configuration
V DD Input/output selection P-ch Pin N-ch V SS CMOS
Output signal Input signal
R
Pull-down resistor N-ch
When KI/O is set to the input mode, pull-down resistor R is turned on.
9
PD61P24
11.3 KI Pin (P12)
This is the 4-bit pin for key input. All of these pins are pulled down to the VSS level by PLA data. Figure 11-2. KI Pin Organization
P2
KI3
KI2
KI1
KI0
11.4
KI Pull-Down Resistor Configuration
V DD
P-ch
Pin PLA KI pull-down resistor switch Pull-down resistor V SS
Input signal
N-ch
V SS
When the pull-down resistor switch is turned on (set 1) by PLA data, pull-down resistor R is turned on.
10
PD61P24
11.5 S-OUT Pin
By going low whenever the carrier frequency is output from the REM pin, the S-OUT pin indicates that communication is in progress. The S-OUT pin is CMOS output. The S-OUT pin goes high on reset. 11.6 S-IN Pin (D0 bit of P1)
To input serial data, use the S-IN pin. When control register (P1) is set to serial input mode, the S-IN pin is connected as an input to the LSB of the accumulator; the S-IN pin is pulled down to the VSS level within the LSI. In this state, if the rotate-left accumulator instruction (RL A) is executed, the data on the S-IN pin is copied to the LSB of the accumulator. If the control register is released from serial input mode, the S-IN pin goes into a high-impedance state, but no through current flows internally. When the RL A instruction is executed, the MSB is copied to the LSB. At reset (all cleared), the S-IN pin goes into a high-impedance state. Figure 11-3. Configuration of the S-IN Pin
CY
A3
A2
A1
A0
S-IN
Control register
11
PD61P24
12. PORT REGISTER (Px)
KI/O, KI, and the control register are handled as port registers. The table below shows the relations between the port registers and pins. Table 12-1. Relations between Port Registers and Pins
Input Mode Read Pin status Pin status Write Output latch - Read Pin status - Output Mode Write Output latch - On Reset Undefined [input mode, output latch] Input mode High impedance (D0 of P1 register = 0)
Pin Name KI/O KI S-IN
Pin status is read by RL A instruction when D0 of P1 register = 1.
P1x (H) K I/O7-4 P 10 Control register (H) P 11 K I3-0 P 12 P 02 P 01 P 00
P0x (L) K I/O3-0 P0
Control register (L)
P1
P2
12
PD61P24
13. CONTROL REGISTER (P1)
The control register contains of 10 bits. The controllable items are shown in Table 13-1. Table 13-1. Control Register (P1)
Bit Name
D9
D8
D7 -
D6 HALT
D5 D.P. AD 9 AD 9 =0 AD 9 =1
D4 D.P. AD 8 AD 8 =0 AD 8 =1
D3 MOD
D2 Timer
D1 K I/O
D0 RL A CC A0 A3 S-IN
Test mode
0 Set Value 1 Be sure to set 0.
NOP OSC STOP
f OSC/8 f OSC/12
STOP RUN
IN OUT
D0 .......................... Specifies data to be input to A0 when the accumulator is shifted to the left. 0: A3, 1:S-IN D1 .......................... Specifies the status of KI/O, as follows: 0: input mode, 1: output mode D2 .......................... Specifies the status of the timer, as follows: 0: Count stop, 1: Count execution D3 .......................... Specifies the carrier frequency output from the REM pin. 0: fOSC/8, 1: fOSC/12 D4, D5 ................. Specify the high-order 2 bits of the ROM data pointer. D6 .......................... Determines what happen to the oscillation circuit when the HALT instruction is executed. 0: Oscillation does not stop 1: Oscillation stops (STOP mode) D7 .......................... Be sure to set this bit to 0. D8, D9 ................. These bits specify test modes. Be sure to set them to 0. Remark D0 = D8 = D9 = 0 on reset, and the other bits are undefined.
13
PD61P24
14. STANDBY FUNCTION (HALT INSTRUCTION)
The PD6600A is provided with the standby mode (HALT instruction), in order to reduce the power consumption, when not executing the program. Clock oscillation can be stopped in the standby mode (STOP mode). In the standby mode, the program execution stops. However, the contents of the internal registers and the data memory are all retained. 14.1 STOP Mode (Oscillation stop HALT instruction)
In the STOP mode, the operation of the system clock generator (ceramic resonator oscillation circuit) stops. Therefore, operations requiring the system clock will stop. If the HALT instruction is executed during timer operation, the program counter stops. The oscillation stop mode will be initiated, after the timer count down operation is completed. 14.2 HALT Mode (Oscillation continue HALT instruction)
The CPU stops its operation, until the HALT release condition is satisfied. The system clock operation continues in this mode. 14.3 Standby Release Conditions
(1) S-IN input (2) KI/O input (3) KI input (4) Timer count down operation completion Remark Either high level or low level can be specified for setting a release condition by input. Table 14-1. Standby Mode Releasing Condition
D3
D2
D1
D0
Releasing Condition S-IN K I/O
Remarks When RL A 3 is selected, the standby mode is always released. Valid only in the IN mode.
0 0
0 0
0 1
0/1
0 0 0
1 1
0 1
KI Timer Released when 0.
Releasing condition:
"0"***Low level detection "1"***High level detection
14
PD61P24
15. AC PIN (ALL CLEAR PIN)
Internal part of the CPU including the program counter can be reset by setting the AC pin to the low level. Watchdog Timer Function A power-on reset function and a CR watchdog timer function, that can be controlled by program, can be realized by connecting a 0.1 F capacitor across the AC pin and the VSS.
Charge mode
V DD
Charge start instruction
0.1 F
Execute HALT instruction immediately before NOP. (Charge for 0.4 ms or more)
Discharge mode Discharge start instruction
0.1 F
Discharge starts after the NOP instruction execution. (Discharge time is about 5 ms from VDD to VthL)
Charge-discharge pattern
V V DD
V thL
The pattern must be controlled by the program, in such a manner that the C charge level will not go below VthL.
t
Caution When the watchdog timer function is not used, switch to charging mode by executing a NOP instruction immediately before a HALT instruction at the beginning of the program. (Be sure to connect the capacitor.)
15
PD61P24
16. MASK OPTIONS (PLA DATA)
The following items are fixed by mask option: * KI, S-IN pin pull-down resistor provided * Carrier duty selection (1/3) at fOSC/12 * Hang-up detection provided <1> KI/O ALL The system is reset when the hang-up detection KI/O ALL switch is set to ON ("1") by PLA data and if the KI/O pins are in the input mode in the oscillation stop HALT mode or if even one of the KI/O pins is low. To use a pin as a key source of the switch, turn ON the switch with PLA data. Figure 16-1. Hang-up Detection KI/O ALL Configuration Diagram
K I/O0 output signal K I/O1 output signal K I/O2 output signal K I/O3 output signal K I/O4 output signal K I/O5 output signal K I/O6 output signal K I/O7 output signal PLA hang-up detection KI/O ALL switch To RESET circuit VDD
KI/O input/output selection
<2> HALT release condition specification (S-IN, KI/O, KI) The system is reset if S-IN and KI/O are used in the HALT mode when S-IN and KI/O are specified by PLA data not to be used ("1"). KI is used ("0").
16
PD61P24
BIT Assignment by Switch Selection
MSB LSB 6 5 4 3 2 1 0
Address
Corresponding Portion
7
0
KI pull-down resistor Note
KI3
KI2
KI1
KI0
0
1 1 1 1 (Provided) (Provided) (Provided) (Provided) 0 0 0 Duty 1 (1/3 duty) KI/O ALL HALT S-IN HALT KI/O 1 (Unused) HALT KI 0 (Used) 0 0 0 S-IN pull-down resistor 1 (Provided) 0
1
Duty S-IN
2
Hang-up detection
1 1 (Detection provided) (Unused)
17
PD61P24
17. WRITING, READING, AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY)
To write, read, or verify the PROM, set the PROM mode and use the pins shown in Table 17-1. No address input pin is used. To update the address, the clock signal input from the CLK pin is used. Table 17-1. Pins Used to Write, Read, and Verify Program Memory
Symbol VPP CLK MD0-MD3 D0-D7 VDD Function Applies program voltage (12.5 V) Inputs clock to update address Selects operation mode Inputs/outputs 8-bit data Applies supply voltage (6 V)
17.1
Operation Mode When Writing, Reading, and Verifying Program Memory
The PD61P24 enters the program memory write, read, or verify mode if +6 V is applied to the VDD pin and +12.5 V is applied to the VPP pin after the reset status has been held a certain time (VDD = 5 V, AC = low level). In this mode, the operation modes listed in Table 17-2 can be selected by using the MD0 through MD3 pins. Any input pins not used for writing, reading, or verifying the program memory must be open or connected to GND via a pull-down resistor (470 ). Table 17-2. Operating Mode When Writing, Reading, and Verifying Program Memory
Specifies Operation Mode VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L x MD2 H H H H MD3 L H H H Clears program memory address to 0 Write mode Read and verify modes Program inhibit mode Operation Mode
x: don't care (L or H)
18
PD61P24
17.2 Program Memory Writing Procedure
The program memory is written at high speed in the following procedure. (1) Pull down the pins not used to GND via resistor. Keep the CLK pin low. (2) Supply 5 V to the VDD pin. Keep the VPP pin low. (3) Wait for 10 s, and supply 5 V to the VPP pin. (4) Set the mode in which the program memory address is cleared to 0, by using the mode setting pins. (5) Supply 6 V to VDD and 12.5 V to VPP. (6) Set the program inhibit mode. (7) Write data in the 1-ms write mode. (8) Set the program inhibit mode. (9) Set the verify mode. If the data has been correctly written, proceed to (10). If not, repeat (7) through (9). (10) Additional writing of (Number of times data has been written in (7) through (9): X) x 1 ms (11) Set the program inhibit mode. (12) Input a pulse four times to the CLK pin to update the program memory address (+1). (13) Repeat (7) through (12) until the data is written to the last address. (14) Set the mode in which the program memory address is cleared to 0. (15) Change the voltage on the VDD and VPP pins to 5 V. (16) Turn off power supply. Program memory writing steps (2) through (12) are illustrated below.
Repeat X times

Reset Write VPP VPP VDD GND VDD VDD+1 VDD GND CLK Verify Additional write
Address increment
D0-D7
Hi-Z
Data input
Hi-Z
Data output
Hi-Z
Data input
Hi-Z
MD0
MD1
MD2
MD3
19
PD61P24
17.3 Program Memory Reading Procedure
(1) Pull down the pins not used to GND via resistor. Keep the CLK pin low. (2) Supply 5 V to the VDD pin. Keep the VPP pin low. (3) Wait for 10 s, and supply 5 V to the VPP pin. (4) Set the mode in which the program memory address is cleared to 0, by using the mode setting pins. (5) Supply 6 V to VDD and 12.5 V to VPP. (6) Set the program inhibit mode. (7) Set the verify mode. If a clock pulse is input to the CLK pin, the data of one address is output each time the pulse has been input to the CLK pin four times. (8) Set the program inhibit mode. (9) Set the mode in which the program memory address is cleared to 0. (10) Change the voltage on the VDD and VPP pins to 5 V. (11) Turn off power supply. Program memory reading steps (2) through (9) are illustrated below.
Reset VPP VPP VDD GND VDD VDD+1 VDD GND CLK
D0-D7
Hi-Z
Data output
Data output
Hi-Z
MD0
MD1
"L"
MD2
MD3
20
PD61P24
18. INSTRUCTION SET
Accumulator Manipulation Instructions
Rr ANL ANL ANL ANL ORL ORL ORL ORL XRL XRL XRL XRL INC RL A, Rr A, @R0H A, @R0L A, #data A, Rr A, @R0H A, @R0L A, #data A, Rr A, @R0H A, @R0L A, #data A A - D10 D30 D31 E00 E10 E30 E31 A00 A10 A30 A31 A13 F13 A01 A02 A0F A20 A21 A2F E01 E02 E0F E20 E21 E2F R10 D00 R11 D01 R12 D02 R1F D0F R00 D20 R01 D21 R0F D2F
Input/Output Instructions
PP IN OUT ANL ORL XRL A, PP , A, A, A, PP A PP PP PP P10 F18 218 D18 E18 A18 P11 F19 219 D19 E19 A19 P12 F1A 21A D1A E1A A1Z P00 F38 238 D38 E38 A38 P01 F39 239 D39 E39 A39 P02 F3A 23A D3A E3A A3A
PP OUT PP #data
P0 318
P1 319
P2 31A
P1P and P0P operate in pair format
Data Transfer Instructions
Rr MOV MOV MOV MOV MOV A, R r A, @R 0 H A, @R 0 H A, #data Rr , A F10 F30 F31 200 201 202 20F 220 221 22F R10 F00 R11 F01 R12 F02 R1F F0F R00 F20 R01 F21 R0F F2F
Rr MOV MOV Rr , #data Rr , @R 0
R0 300 320
R1 301 321
R2 302 322
RF 30F 32F
R1r and R0r operate in pair format
21
PD61P24
Branch Instructions
Rr JMP0 JMP0 JC JC JNC JNC JF JF JNF JNF addr RrNote addr RrNote addr RrNote addr RrNote addr RrNote - 411 - 611 - 631 - 711 - 731 - - 721 722 72F - 701 702 70F - 621 622 62F - 601 602 60F - 401 402 40F R0 R1 R2 RF Pair register
Note
r = 1 through F r = 0 canot be used.
Subroutine Instructions
PP CALL0 RET addr P0 312 412 P1 411
Timer/Counter Manipulation Instructions
Tt MOV MOV MOV MOV A, Tt Tt , A T, T, #data @R 0 T0-1 - 31F 33F T1 F1F 21F T0 F3F 23F
Other Instructions
R 00 HALT #data STTS R 0r STTS #data SCAF NOP 111 120 131 D13 000 121 122 12F R 01 R 02 R 0F
22
PD61P24
19. APPLICATION CIRCUIT EXAMPLE
Key matrix
1 VDD VDD 2 3 Infrared LED
SE303 series SE313 SE307-C SE1003-C
KI/O1 KI/O0 S-IN
KI/O2 KI/O3 KI/O4 KI/O5
20 19 18 17 16 15 Mode select switch 14 13 12 11
Transmission indication
4
S-OUT
KI/O6 KI/O7
2SC3616, 3618 2SD1615, 1616 2SC2001 100 pF 3.0 V 100 pF
5 6 7 8 47 F + 9 10 0.1 F
REM VDD OSC-OUT OSC-IN VSS AC KI0 KI1 KI2 KI3
PD61P24
Caution The ceramic resonator start up capacitor value must be determined, by taking the voltage level and the oscillation start up characteristics for the ceramic resonator into consideration.
23
PD61P24
20. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 C)
Parameter Supply Voltage Input Voltage Operating Ambient Temperature Storage Temperature Symbol VDD VIN TA Tstg Ratings 7.0 -0.3 to VDD + 0.3 -20 to +75 -40 to +125 Unit V V C C
Caution
Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure to use the product(s) within the ratings.
Recommended Operating Range (TA = 25 C)
Parameter Supply Voltage Oscillation Frequency Symbol VDD fOSC MIN. 2.2 400 TYP. MAX. 5.5 500 Unit V kHz
24
PD61P24
DC Characteristics (VDD = 3.0 V, fOSC = 455 kHz, TA = 25 C)
Parameter Supply Voltage Current Consumption 1 Current Consumption 2 REM High Level Output Current REM Low Level Output Current S-OUT High Level Output Current S-OUT Low Level Output Current KI High Level Input Current KI High Level Input Current KI Low Level Input Current KI/O High Level Input Current KI/O High Level Input Current KI/O Low Level Input Current KI/O High Level Output Current KI/O Low Level Output Current S-IN High Level Input Current S-IN High Level Input Current S-IN Low Level Input Current KI High Level Input Voltage KI Low Level Input Voltage KI/O High Level Input Voltage KI/O Low Level Input Voltage S-IN High Level Input Voltage S-IN Low Level Input Voltage AC Pull-Up Resistor AC Pull-Down Resistor AC High Level Input Voltage AC Low Level Input Voltage Symbol VDD IDD1 IDD2 IOH1 IOL1 IOH2 IOL2 IIH1 IIH1' IIL1 IIH2 IIH2' IIL2 IOH3 IOL3 IIH3 IIH3' IIL3 VIH1 VIL1 VIH2 VIL2 IIH3 IIL3 R1 R2 VIH4 VIL4 VI = 0 V VI = 2.7 V VI = 3.0 V fOSC = 455 kHz fOSC = STOP VO = 1.0 V VO = 0.3 V VO = 2.7 V VO = 0.3 V VI = 3.0 V VI = 3.0 V, without pull-down resistor VI = 0 V VI = 3.0 V VI = 3.0 V, without pull-down resistor VI = 0 V V0 = 2.5 V V0 = 2.1 V VI = 3.0 V VI = 3.0 V, without pull-down resistor VI = 0 V 2.1 0 1.3 0 1.1 0 0.3 150 1.8 0 400 -1.5 25 6 -2.0 50 10 -5 0.5 -0.3 1 10 -8 1.5 -1.0 1.5 Conditions MIN. 2.2 0.3 TYP. MAX. 5.5 1.5 1.0 -15 2.5 -2.0 2.5 30 0.2 -0.2 30 0.2 -0.2 -4.0 100 15 0.2 -0.2 3.0 0.9 3.0 0.4 3.0 0.4 3.0 1500 3.0 1.2 Unit V mA
A
mA mA mA mA
A A A A A A
mA
A A A A
V V V V V V k k V V
25
PD61P24
DC Programming Characteristics (TA = 255 C, VDD = 6.00.25 V, VPP = 12.50.5 V)
Parameter High-level input voltage Symbol VIH1 VIH2 Low-level input voltage VIL1 VIL2 Input leakage current High-level output voltage Low-level output voltage VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Conditions Other than CLK CLK Other than CLK CLK VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD-1.0 0.4 30 30 MIN. 0.7 VDD VDD-0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. Keep VPP to within +13.5 V including the overshoot. 2. Apply VDD before VPP, and turn it off after VPP. AC Programming Characteristics (TA = 255 C, VDD = 6.00.25 V, VPP = 12.50.5 V)
Parameter Address setup timeNote 2 (vs. MD0) Symbol tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tM0S tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR tRES Note 1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR -- -- -- -- -- -- -- tACC tOH -- -- On reading program memory On reading program memory On reading program memory On reading program memory On reading program memory 10 0 2 2 2 2 2 2 2 130 MD0 = MD1 = VIL tM1H + tM1R 50 s 2 2 10 0.125 4.19 Conditions MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2 1 1.0 1.05 21.0 130 TYP. MAX. Unit
s s s s s
ns
MD1 setup time (vs. MD0) Data setup time (vs. MD0) Address hold timeNote 2 (vs. MD0)
Data hold time (vs. MD0) MD0 data output float delay time VPP setup time (vs. MD3) VDD setup time (vs. MD3) Initial program pulse width Additional program pulse width MD0 setup time (vs. MD1) MD0 data output delay time MD1 hold time (vs. MD0) MD1 recovery time (vs. MD0) Program counter reset time CLK input high-, low-level widths CLK input frequency Initial mode set time MD3 setup time (vs. MD1) MD3 hold time (vs. MD1) MD3 setup time (vs. MD0) AddressNote 2 AddressNote 2 data output delay time data output hold time
s s
ms ms
s s s s s s
MHz
s s s s s
ns
MD3 hold time (vs. MD0) MD3 data output float delay time Reset setup time
s s s
Notes 1. Corresponding symbols of PD27C256A (the PD27C256A is a maintenance product). 2. The internal address signal is incremented by one at the falling edge of CLK input at the third clock.
26
PD61P24
PROGRAM MEMORY WRITE TIMING
VPP
VPP VDD GND VDD+1 VDD GND CLK
tRES
tVPS
tVDS tXH
VDD
D0-D7
Hi-Z tI
Data input tDS tOH
Hi-Z
Data output tDV tDF
Hi-Z
tXL Data input tDS tDH tAH tOPW
Hi-Z tAS
Data input
Hi-Z
MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1S tM1H tM1R tM0S
PROGRAM MEMORY READ TIMING
tRES tVPS VPP VPP VDD GND VDD+1 VDD GND CLK tXL D0-D7 tI MD0 Hi-Z tDV Data output tDAD tHAD Data output tM3HR Hi-Z tDFR tVDS tXH
VDD
MD1 tPCR MD2 tM3SR MD3
"L"
27
PD61P24
21. PACKAGE DRAWINGS
20 PIN PLASTIC SOP (300 mil)
20 11 detail of lead end
1 A
10 H
G
P
I
J
F
K
E
C D
NOTE
N M
M
B
L
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 13.00 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 -0.05 0.10.1 1.8 MAX. 1.55 7.70.3 5.6 1.1 0.20 +0.10 -0.05 0.60.2 0.12 0.10 3 +7 -3
INCHES 0.512 MAX. 0.031 MAX. 0.050 (T.P.) 0.016 +0.004 -0.003 0.0040.004 0.071 MAX. 0.061 0.3030.012 0.220 0.043 0.008 +0.004 -0.002 0.024 +0.008 -0.009 0.005 0.004
3 +7 -3
Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
P20GM-50-300B, C-4
28
PD61P24
20PIN PLASTIC SHRINK DIP (300 mil)
20 11
1
A I
10
K L
J
H G F D N
M
C B M R
NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition.
2) ltem "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 19.57 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.85 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 7.62 (T.P.) 6.5 0.25 +0.10 -0.05 0.17 0~15
INCHES 0.771 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.033 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.300 (T.P.) 0.256 0.010 +0.004 -0.003 0.007 0~15 P20C-70-300B-1
29
PD61P24
22. RECOMMENDED SOLDERING CONDITIONS
It is recommended that PD6124A and 6600A be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document, Semiconductor Device Mounting Technology Manual (C10535E). For other soldering methods and conditions, consult NEC. Table 22-1. Soldering Conditions of Surface-Mount Type
PD61P24GS: 20-pin plastic SOP (300 mil)
Soldering Method Partial Heating Soldering Conditions Pin temperature: 300C max., time: 3 seconds max. (per device side)
Table 22-2. Soldering Conditions of Through-Hole Type
PD61P24CS: 20-pin plastic shrink DIP (300 mil)
Soldering Method Wave Soldering (Only for pin part) Partial Heating Soldering Conditions Solder bath temperature: 260C max., time: 10 seconds max. Pin temperature: 300C max., time: 3 seconds max. (per pin)
Caution When soldering this product using of wave soldering, exercise care that the solder does not come in direct contact with the package.
30
PD61P24
APPENDIX A. PD612x SERIES PRODUCT LIST
Part Number Item ROM capacity
PD6124A
1002 x 10 bits (mask ROM) 32 x 5 bits 8 pins (KI/O0-7)
PD6600A
512 x 10 bits (mask ROM)
PD61P24
PD6125A
PD6126A
1002 x 10 bits 1002 x 10 bits (one-time PROM) (mask ROM)
RAM capacity I/O pin
12 pins (KI/O0-7, I/O00-03)
16 pins (KI/O0-7, I/O00-03, I/O10-13)
S-IN pin Current consumption (fOSC = STOP) (MAX.) S-IN high-level input current (MAX.)
Provided 2 A 30 A 1 A 15 A
Transmission carrier frequency fOSC/12, fOSC/8 Low-voltage detection (reset) function Mask option Supply voltage Package Provided None
Provided
None (fixed)
Provided
VDD = 2.2 to 5.5 V VDD = 2.2 to 3.6 V VDD = 2.2 to 5.5 V VDD = 2.0 to 6.0 V * 20-pin plastic SOP (300 mil) * 20-pin plastic shrink DIP (300 mil) * 24-pin plastic SOP (300 mil) * 24-pin plastic shrink DIP (300 mil) * 28-pin plastic SOP (375 mil)
31
PD61P24
APPENDIX B. DEVELOPMENT TOOLS
The following tools are available for program development using the PD61P24.
Document Document No. --Note 1 --Note 1 AF-9703Note 2, 3 AF-9704Note 2, 3 AF-9705Note 3 AF-9706Note 3 AF9807BNote 3
PS612X Series Emulator PS61P24 Assembler
PROM Programmer
PD61P24 Program Adapter
Notes 1. These are products from I.C Corp. For details, consult I.C Corp. I.C Corp. 6th Barnet Gotanda Bldg. 1-9-5 Higashi-Gotanda, Shinagawa-ku, Tokyo 141 Tel. 03-3447-3793 Fax. 03-3440-5606 2. Not available. 3. These are products from Ando Electric Co., Ltd. For details, consult Ando Electric Co., Ltd. Ando Electric Co., Ltd. 4-19-7 Kamata, Ota-ku, Tokyo 144 Tel. 0120-40-0211(toll-free) Caution Use a writing program after assembling the program, convert the HEX file to a ROM file by using the PROM utility program "UPDPROM" (refer to AS612X Assembler User's Manual(IEM-1016)).
32
PD61P24
[MEMO]
33
PD61P24
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
34
PD61P24
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
35
PD61P24
[MEMO]
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
36

▲Up To Search▲

Price & Availability of UPD61P24

	To Download UPD61P24 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .